The present embodiments relate to data converters, and are more particularly directed to an analog-to-digital converter based in part upon a digital-to-analog converter.
Data converters may be used in various types of electronic circuits, or may be formed as a single integrated circuit device. Such converters typically take one of two forms, either as a digital-to-analog converter ("DAC") or an analog-to-digital converter ("ADC"). For the DAC, its operation converts an input digital signal to an output analog signal, typically where the amplitude of the output analog signal corresponds directly to the magnitude of the input digital signal. Conversely, the ADC converts an input analog signal to an output digital signal, typically where the value of the output digital signal corresponds directly to the amplitude of the input analog signal. In many configurations, both DACs and ADCs implement a resistor string that includes a number of series-connected resistors, where each resistor provides a voltage tap at each of its ends. Typically, the overall string is biased at opposing ends by two different reference voltages, where for example one such voltage is a positive voltage and the other is ground. Also in this regard, in an effort to maintain the linearity between the digital input and the analog output, a common concern in the art is to endeavor to ensure that each resistor in the string has as close to the same resistance value as all other resistors in the string. Accordingly, the resistor string forms a series voltage dividing network and each of the voltage taps is accessible as part of the operation for the data conversion (i.e., either from digital to analog, or analog to digital).
For further background to converters, it is noted that often ADCs are formed using one or more stages that include a DAC for each stage. Accordingly, by way of further introduction and example, FIG. 1 illustrates a typical configuration of a prior art DAC 10, and is detailed briefly below. Once an understanding for such a DAC is presented, additional aspects are treated whereby such a DAC is used in the prior art to form an ADC.
FIG. 1 illustrates a typical configuration of a prior art DAC 10, and is detailed briefly here with additional detail ascertainable by one skilled in the art. By way of example and as appreciated later, DAC 10 is a 4-input 16-output DAC, while numerous other dimensions may exist for different DAC configurations. In general and as detailed below, DAC 10 is operable to receive a 4-bit input word, designated from least significant bit to most significant bit as I.sub.0 -I.sub.3. In response to the magnitude of these bits, DAC 10 outputs a corresponding analog voltage. Before detailing this operation, it is first instructive to examine the devices and connections of DAC 10. In this regard, DAC 10 includes a series-connected resistor string designated generally at 12, and that forms a meander in that it serpentines back and forth. Additionally, DAC 10 is generally a symmetric array in nature, having a number of bit lines in the vertical dimension and a number of word lines in the horizontal dimension. Since the example of DAC 10 presents a 4input 16-output DAC, the array of DAC 10 includes four bit lines BL0 through BL3, and four word lines WL0 through WL3. Also for the current example of a 4-to-16 DAC, resistor string 12 includes fifteen resistive elements R0 through R14. Resistive elements R0 through R14 may be formed using various techniques, where regardless of the technique ideally each resistive element has as close to the same resistance value as all other resistors in the string. Moreover, a voltage source V.sub.REF1 is applied across resistor string 12, and may be of any suitable biasing voltage, which for current applications is typically on the order of 2.0 volts. For DAC 10, string 12 is biased between V.sub.REF1 and ground, but it should be understood that in other configurations two different non-ground potentials may be connected at opposing ends of string 12. When ground is connected to one end of the string, it is easily appreciated that this difference of the potentials at the ends of the string equals V.sub.REF1. In any event, given the equal resistance of each element in the string, V.sub.REF1 is uniformly divided across the resistive elements of string 12.
Looking to the detailed connections with respect to resistive elements R0 through R14, each resistive element provides two taps and, therefore, two voltages that may be sampled as detailed below. For example, looking to resistive element R0, it provides a tap T0 and a tap T1, while resistive element R1 shares the same tap T1 and provides another tap T2, and so forth. Each tap has a switching device connected between it and a corresponding output bit line. In the current example, each of these switching devices is an n-channel field effect transistor, and is labeled for convenience by combining the abbreviation ST (i.e., switching transistor) with the same numeric identifier corresponding to the tap to which a source/drain of the transistor is connected. For example, a source/drain of transistor ST0 is connected to tap T0, a source/drain of transistor ST1 is connected to tap T1, and so forth. Further, the switching transistors are arranged so that a like number of taps are coupled via corresponding switching transistors to a corresponding one of the bit lines. In the current example of DAC 10, four taps are coupled in this manner to a corresponding bit line. For example, taps T0 through T3 are coupled, via corresponding switching transistors ST0 through ST3, to bit line BL0. As another example, taps T4 through T7 are coupled, via corresponding switching transistors ST4 through ST7, to bit line BL1. Each bit line BL0 through BL3 is coupled to a first source/drain of a respective column access transistor, CAT0 through CAT3, where the second source/drains of the column access transistors are connected to the output V.sub.OUT1. In addition, column decoder 14 is coupled to receive the two most significant bits (MSBs) of the 4-bit word input to DAC 10, and in response column decoder 14 controls the gates of column access transistors CAT0 through CAT3.
Returning now to switching transistors ST0 through ST15, and given the array nature of DAC 10, it is further appreciated that the switching transistors are arranged so that a like number of switching transistors are controlled, via connection to their gates, by a corresponding word line that is further connected to row decoder 16. Given the current example of DAC 10, the gates of four switching transistors are coupled to each corresponding word line. For example, the gates of switching transistors ST0, ST7, ST8, and ST15 are coupled to word line WL0. As another example, the gates of switching transistors ST1, ST6, ST9, and ST14 are coupled to word line WL1. Lastly in this regard, and for reasons evident below, row decoder 16 is coupled to receive the two least significant bits (LSBs) of the 4-bit word input to DAC 10 (i.e., bits I.sub.1 and I.sub.0), and is also controlled in response to the least significant bit ("Isb"), I.sub.2, of the two MSBs input to column decoder 14. More particularly, each least significant bit I.sub.0 and I.sub.1 is coupled as an input to a corresponding exclusive OR gate EOG0 and EOG1 as a first input, while the second input of exclusive OR gates EOG0 and EOG1 is connected to receive 12 (i.e., the least significant bit of the two MSBs input to column decoder 14). In response to these bits, row decoder 16 controls the gates of switching transistors ST0 through ST15 as detailed below.
The operation of DAC 10 is now described, first in general and then more specifically through the use of a few examples. A 4-bit digital word is connected to inputs I.sub.0 through I.sub.3 and ultimately causes signals to pass to column decoder 14 and row decoder 16. Generally, row decoder 16 includes sufficient logic circuitry or the like to respond by identifying/asserting one of word lines WL0 through WL3, thereby providing an enabling voltage to the gates of the four switching transistors coupled to the asserted word line. Similarly, column decoder 14 includes sufficient logic circuitry or the like to respond by identifying/enabling one of column access transistors CAT0 through CAT3, thereby causing the enabled transistor to pass the voltage from the corresponding one of bit lines BL0 through BL3 to output V.sub.OUT1. In a simple case, the result of the above operations may be viewed by correlating the value of the 4-bit input to one of the sixteen decimal tap numbers. For example, if the 4-bit digital word equals 0001 (i.e., decimal value one), then DAC 10 enables a switching transistor and a column access transistor to couple the voltage at tap T1 to V.sub.OUT1.
By way of detailed illustration of the operation of DAC 10, the example of an input equal to 0001 is now traced through DAC 10 in greater detail. From the input of 0001, its two MSBs are coupled to column decoder 14 and, thus, the value of 00 is received by column decoder 14. In response, column decoder 14 enables the gate of the column access transistor having a numeric identifier equal to the decimal value of the MSBs. Here, the MSBs of 00 equal a decimal value of zero and, thus, column decoder 14 couples an enabling voltage to the gate of column access transistor CAT0. Turning now to row decoder 16, it responds to the value of the two LSBs of the 4-bit input. However, note that these two LSBs pass through exclusive OR gates and, therefore, their values are unchanged when passed to row decoder 16 if the lsb equals 0, or their complements are passed to row decoder 16 if the lsb equals 1. Returning then to the example of a 4-bit input equal to 0001, the two LSBs equal 01 and the lsb of the two MSBs equals 0. Thus, the unchanged LSBs equal to 01 reach row decoder 16, and row decoder 16 in response asserts the word line having a decimal numeric identifier equal to the value of the two LSBs as received from gates EOG0 and EOG1. In the present example, therefore, row decoder 16 asserts word line WL1 high which, therefore, enables each of switching transistors ST1, ST6, ST9, and ST14. Recall also that column decoder 14 in this example enables column access transistor CAT0. As a result, the voltage from tap T1 passes via switching transistor ST1 to bit line BL0, and then passes via column access transistor CAT0 to output V.sub.OUT1. Lastly, it is noted that the voltage at tap T1 is divided across one resistive element (i.e., R0) and, thus, for an input equal to 0001, the analog output voltage using voltage division is 1/15*V.sub.REF1.
To further illustrate in detail the operation of DAC 10, consider now the example of a digital input equal to 0111 as traced through DAC 10. At the outset, from the general operation described above, one skilled in the art will expect that since the decimal value of 0111 equals seven, then the tap selected by DAC 10 for output is tap T7. This expectation is now confirmed through a detailed examination of this example. From the input of 0111, its two MSBs of 01 are coupled to column decoder 14. In response, column decoder 14 enables the gate of the column access transistor having a decimal numeric identifier equal to the two MSB values of 01 and, hence, the gate of column access transistor CAT1 is enabled. Turning now to row decoder 16, note first that the lsb of the two MSBs in this example equals one; consequently, gates EOG0 and EOG1 cause the complements of the two LSBs to reach row decoder 16. Thus, the complements of the 11 LSBs are 00 and, therefore, the value of 00 reaches row decoder 16. In response, row decoder 16 asserts word line WL0 high since that word line has a numeric identifier equal to the value of the two complemented LSBs. When word line WL0 is asserted, it enables each of switching transistors ST0, ST7, ST8, and ST15. Recall also that column decoder 14 in this example enables column access transistor CAT1. As a result, the voltage from tap T7 passes via switching transistor ST7 to bit line BL1, and then passes via column access transistor CAT1 to output V.sub.OUT1. Lastly, it is noted that the voltage at tap T7 is divided across seven of the fifteen resistive elements (i.e., R0 through R6) and, thus, for an input equal to 0111, the analog voltage output using voltage division is equal to 7/15*V.sub.REF1. Accordingly, the digital input of 0111 has been converted to an analog voltage which equals this divided voltage. Given this as well as the preceding example, one skilled in the art will further appreciate that with different digital inputs, any of the switching transistors of DAC 10 may be enabled along with enabling one of the column access transistors, and for each such combination of transistors there is a corresponding output that represents a divided voltage between zero volts or any value incrementing up from zero volts by 1/15V.sub.REF1, and up to an output equal to V.sub.REF1.
FIG. 2 illustrates a block diagram of a prior art ADC 20, and which incorporates DAC 10 of FIG. 1. ADC 20 receives an analog input voltage V.sub.IN1, at an input 22 to a comparator 24, where in the example of FIG. 2 it is assumed that V.sub.IN1 is equal to or greater than ground. Input 22 is connected to the non-inverting input of comparator 24, and the inverting input 26 of comparator 24 is connect ed to receive the output voltage from output V.sub.OUT1 of DAC 10. ADC 20 further includes a successive approximation register ("SAR") 28, having an input 30 connected to the output of comparator 24. Lastly, and in response to a clocked methodology described below, SAR 28 outputs a digital word along an address bus 32, where that digital word is connected to the input of DAC 10 and ultimately may be sampled to indicate the converted digital output, V.sub.OUTD1, for ADC 20.
The operation of ADC 20 is as follows. In general, ADC 20 operates to convert an input analog voltage to an output digital value and, therefore, here the conversion is from the signal V.sub.IN1 to the value V.sub.OUT1. By way of example, and recalling that DAC 10 is a 4-bit device, then assume further that ADC 20 is likewise a 4-bit device, that is, the converted output value V.sub.OUTD1 is a 4-bit word shown in FIG. 2 having bits I.sub.0 through I.sub.3. Turning to the operation in greater detail, initially the analog voltage V.sub.IN1 is coupled to input 22, and a first clock signal is applied to SAR 28 to commence a sequence of operations. SAR 28 operates such that, for each successive clock to it, it performs a binary search routine in view of the feedback it receives from comparator 24. Binary search routines are generally known in the art and, in that regard, such a routine first determines the most significant bit of the eventual output (i.e., bit I.sub.3) and with each successive clock cycle determines the next least significant bit of the eventual output. Further in this regard, note that while not shown, preceding ADC 20 (or as a part of it) there is included some type of sample-and-hold circuit. As appreciated from the following description, this sample-and-hold circuit maintains the input value for a necessary number of clock cycles while the binary search routine determines the final output. For the example of ADC 20, four total clock cycles are required to determine each of the four output bits in the converted output signal V.sub.OUTD1 and, thus, the sample-and-hold circuit maintains the input voltage to ADC 20 during this determination. If required by the reader, this process is detailed still further immediately below.
To further demonstrate the operation of ADC 20 and the method of a binary search routine, the following discussion traces a n example whereby ADC 20 converts an incoming analog voltage to a digital value of 1011. In other words, for the following example, the magnitude of the analog input voltage is such that it should correspond to a digital value of 1011. As mentioned above, the determination of each of the four output bits requires a separate clock cycle of operation. Accordingly, each of these four clock cycles is discussed below.
In response to the first clock assertion to SAR 28, SAR 28 outputs a 4-bit address on bus 32, with the MSB of that address set to a logic high and leaving the remaining LSBs set to low. Thus, for this first clock assertion a digital value of 1000 is placed on bus 32. This value of 1000 is input to DAC 10 which, according to the techniques described earlier with respect to FIG. 1, outputs a corresponding analog voltage at output V.sub.OUT1. Here, the V.sub.OUT1 voltage is input to comparator 26, which therefore compares V.sub.OUT1 with V.sub.IN1 (i.e., the analog voltage being converted). The result of this comparison is fed back to SAR 28, and is either positive or negative based on the comparison. Recall that in the current example, the ultimate digital output is 1011. Accordingly, for this first clock cycle the comparison indicates that V.sub.IN1 is greater than V.sub.OUT1 because comparator 24 is comparing an analog voltage V.sub.IN1 having a magnitude corresponding to a value of 1011 to an analog voltage V.sub.OUT1 having a magnitude, as provided by DAC 10, corresponding to a value of 1000. In response to the positive output of comparator 24, it is concluded by SAR 28 that the digital output word corresponding to V.sub.IN1 should be higher than the current word on bus 32, that is, the ultimate value Of V.sub.OUTD1 is greater than the address 1000 currently on bus 32. By way of alternate example, if after this first clock cycle the comparison indicates that V.sub.IN1 is less than V.sub.OUT1, then it is concluded by SAR 28 that the digital word corresponding to V.sub.IN1 should be lower than 1000. Returning now to the example of an analog input corresponding to a value of 1011, however, the first clock cycle results in a determination that the ultimate output exceeds 1000. Accordingly, at this point SAR 28 maintains a record that the MSB should be set to 1, thereby ensuring that the ultimate value Of V.sub.OUT1 as may be sampled from bus 32 is equal to or greater than 1000 as appreciated from the remaining discussion of FIG. 2.
Following the above, a second clock cycle is asserted to SAR 28, and SAR 28 responds by repeating the preceding steps but here with respect to the next lesser significant bit of its four bit analysis and also in view of what already has been determined with respect to the MSB. Specifically, and continuing with the present example, in response to the second clock assertion SAR 28 again outputs a 4-bit address on bus 32, with the MSB set to the value recorded from the first clock (i.e., 1 in the current example). In addition, SAR 28 sets the next lesser significant bit (i.e., I.sub.2) to a logic high and again leaves the remaining LSBs set to low. Thus, for this second clock assertion a digital value of 1100 is placed on bus 32 and thereby input to DAC 10. In response, DAC 10 outputs a corresponding analog voltage V.sub.OUT1 to comparator 24, which therefore compares V.sub.OUT1 With V.sub.IN1 (i.e., the analog voltage being converted) and feeds back the comparison result to SAR 28. Recall that in the current example, the ultimate digital output is 1011. Accordingly, for this second clock cycle the comparison indicates that V.sub.IN1 is lower than V.sub.OUT1 because comparator 24 is comparing an analog voltage V.sub.IN1 having a magnitude corresponding to a value of 1011 to an analog voltage V.sub.OUT1 having a magnitude, as provided by DAC 10, corresponding to a value of 1100. In response to the negative output of comparator 24, it is concluded by SAR 28 that the digital output word corresponding to V.sub.IN1 should be lower than the current word on bus 32, that is, the ultimate value of V.sub.OUTD1 is less than 1100. Accordingly, at this point SAR 28 maintains a record that the MSB should be set to 1, and the next lesser significant bit should be set to 0, thereby ensuring that the ultimate value of V.sub.OUTD1, as may be sampled from bus 32, will have its two MSBs equal to or greater than 10.
Continuing with the third clock cycle asserted to SAR 28, SAR 28 again repeats the above, now with respect to the next lesser significant bit of the four bits and, hence, with respect to bit I.sub.1. Continuing again with the present example, in response to the third clock assertion SAR 28 again outputs a 4-bit address on bus 32, with the two most MSBs set to the values recorded from the first and second clock (i.e., 10 in the current example). In addition, SAR 28 sets the next lesser significant bit (i.e., I.sub.1) to a logic high and again leaves the least significant bit set to zero. Thus, for this third clock assertion a digital value of 1010 is placed on bus 32 and thereby input to DAC 10. In response, DAC 10 outputs a corresponding analog voltage V.sub.OUT1 to comparator 24, which therefore compares V.sub.OUT1 with V.sub.IN1 and feeds back the comparison result to SAR 28. Recall that in the current example, the analog input V.sub.IN1 corresponds to 1011. Accordingly, for this third clock cycle the comparison indicates that V.sub.IN1 is greater than V.sub.OUT1. In response to the positive output of comparator 24, it is concluded by SAR 28 that the digital output word corresponding to V.sub.IN1 should be higher than the current word on bus 32, that is, the ultimate value of V.sub.OUTD1 is greater than 1010. Accordingly, at this point SAR 28 maintains a record that the three MSBs should be set to 101, thereby ensuring that the ultimate value of V.sub.OUTD1 as may be sampled from bus 32 is equal to or greater than 1010.
The fourth and final clock cycle asserted to SAR 28 completes the LSB of the 4-bit output of ADC 20 by repeating steps comparable to the above. Thus, with respect to bit I.sub.0 and in response to the fourth clock assertion SAR 28 again outputs a 4-bit address on bus 32, with the three most MSBs set to the values recorded from the first through third clock cycles (i.e., 101 in the current example). In addition, SAR 28 sets the next lesser significant bit (i.e., I.sub.0) to a logic high. Thus, for this fourth clock assertion a digital value of 1011 is placed on bus 32 and thereby input to DAC 10. In response, DAC 10 outputs a corresponding analog voltage V.sub.OUT1 to comparator 24, which therefore compares V.sub.OUT1 with V.sub.IN1 (i.e., the analog voltage being converted) and feeds back the comparison result to SAR 28. Recall that in the current example, the ultimate digital output is 1011. Accordingly, for this fourth clock cycle the comparison indicates either that V.sub.IN1 equals V.sub.OUT1 or, in a more likely statistical case, that V.sub.IN1 slightly exceeds V.sub.OUT1. In response to the positive output of comparator 24 with respect to this final bit, it is concluded by SAR 28 that the digital output word corresponding to V.sub.IN1 is that which is currently being input on address bus 32 to DAC 10. Accordingly, at this point the address of 1011 on bus 32 is available for sampling at output V.sub.OUTD1 of ADC 20 and as such represents the final converted value for the current example. Lastly, it should be noted with respect to the final bit that if the comparison were such that the value V.sub.OUT1 from DAC 10 were lower than V.sub.IN1, then SAR 28 sets the value of I.sub.0 to 0 and outputs that newly adjusted address to bus 32, in which case for the current example a converted value of 1010 would have been output as the final digital conversion.
While ADC 20 of FIG. 2 has provided useful in various configurations, the present inventors have recognized various of its drawbacks where such drawbacks may render an alternative embodiment more desirable in certain instances. For example, as stated by introduction and shown through the preceding example, to perform its conversion ADC 20 requires a number of clock cycles equal to the number of output bits. For larger ADCs, therefore, the number of clock cycles is correspondingly large. In addition, this limitation is combined with the use of a resistor string 12 which may be slower than other implementations due to the time required by decoders 14 and 16 as well as any resistive/capacitive delay introduced by the overall circuit configuration.
By way of further background, an alternative ADC configuration is known in the art which is sufficiently simple in construction to describe without illustration. In the alternative, again a resistor string is implemented whereby each tap along the string corresponds to a different analog voltage. Each tap is connected to a first input of a corresponding comparator, while the second input of each comparator is connected to receive the to-be-converted analog voltage. Thus, when the analog input voltage is input to the ADC, in a single instance, sometimes referred to as a flash, the voltage is compared by the numerous comparators to each tap voltage. At some point along the successive comparators, the output of one comparator will differ from the output of the next successive comparator. Thus, the input voltage is between the tap voltages corresponding to these two different comparators, and this location is then encoded to present a digital value corresponding to this location. While this alternative operates as a flash device, the present inventors also have recognized many of its drawbacks. For example, the number of comparators increases exponentially with the bit size of the ADC, that is, it equals the number of taps in the string. For example, an 8-bit ADC of this type may select among 256 different voltages and, thus, requires at least 256 comparators. As another example of a drawback, for each of these comparators, they will require strict offset limitations to ensure that the comparator offset is considerably less than the difference between tap voltages. This requirement increases both device complexity and cost, and may be particularly troublesome where a large number of comparators are required. As still another example, a total flash architecture requires that the input voltage drive an input capacitance of all of the comparators in parallel. Thus, in the 8-bit ADC with 256 comparators, the input voltage must drive the capacitance of all of these comparators. This level of capacitance is relatively large, and may be quite a burden on a high speed pin.
In view of these preceding embodiments and drawbacks as well as others ascertainable by one skilled in the art, there arises a need to provide an improved ADC as is achieved by the preferred embodiments discussed below.